Last week, Western Digital made Verilog sources for its open source RISC-V core publically available on GitHub under Apache 2.0.
What is SweRV Core?
‘SweRV Core’ was made by Western Digital for internal use which they decided to contribute to the open source community. The SweRV Core is a 32-bit, nine stage pipeline core which is two-way superscalar. It is small in size and has a simulation performance of up to 4.9 CoreMarks/Mhz. SweRV Core comes supports data-intensive applications like storage controllers, industrial IoT devices, real-time analytics in surveillance systems etc., Running on a 28mm CMOS battery, the power-efficient design has clock speeds up to 1.8Ghz. This core will be seen in future and upcoming WD products.
Martin Fink, CTO of Western Digital, says to the Business Wire: “As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today’s wide-ranging data-centric applications. Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power.”
What do you need for SweRV Core?
- Verilator 3.926 or newer
- Espresso needs to be installed if you want to add or remove instructions
To start using it, Core clone the GitHub repo, setup RV_ROOT pointing to the path of your system, and run make with tools/Makefile.
Last year Western Digital had also open-sourced SweRV Instruction Set Simulator (ISS). It is a program for designers to simulate code on SweRV core. Optionally, you can determine your config before running make.
To get started, you can check out the GitHub repository.